Fabrication method of semiconductor device having dual gate oxide layer

专利摘要:
PURPOSE: A method for fabricating a semiconductor device having a dual gate oxide layer is provided to prevent contamination of a gate oxide layer by improving the fabricating method of the semiconductor device. CONSTITUTION: A trench oxide layer(53) is formed on a substrate(51). The first silicon oxide layer is formed on the whole surface of the substrate(51). The first conductive layer is formed on the first silicon oxide layer. The first insulating layer is formed on the first conductive layer. A gate pattern(61) and a gate oxide layer(55a) are formed by patterning the first insulating layer, the first conductive layer, and the first silicon oxide layer. The first dopant region(63) is formed on the substrate(51). A spacer(65) is formed on both sidewalls of the gate pattern(61) and the gate oxide layer(55a). The second dopant region(67) is formed on the substrate(51). A source/drain region(68) is formed by the first and the second dopant region(63,67). The second insulating layer is formed on the whole surface of the substrate(51). The third insulating layer is formed on the whole surface of the substrate(51). An interlayer dielectric is formed by planarizing the third insulating layer. An interlayer dielectric pattern(71b) having a contact hole and the second insulating layer pattern(69a) are formed by etching the interlayer dielectric and the second insulating layer. The second silicon oxide layer(79) is formed by using a thermal oxidation method.
公开号:KR20030001827A
申请号:KR1020010037634
申请日:2001-06-28
公开日:2003-01-08
发明作者:조창현；조민희；김기남
申请人:삼성전자 주식회사；
IPC主号:

专利说明:

Fabrication method of semiconductor device having a double gate oxide layer {Fabrication method of semiconductor device having dual gate oxide layer}
[5] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a double gate oxide film.
[6] As the semiconductor devices are highly integrated, the size of transistors is decreasing. In particular, as the gate length decreases, the thickness of the gate oxide layer must also be reduced to improve the operation speed of the semiconductor device. However, when the thickness of the gate oxide film is reduced, the possibility of breakdown of the gate oxide film increases.
[7] On the other hand, semiconductor devices such as DRAM devices, etc., have an increasing share of the cell array area in the chip. As a result, when all the gate oxide film thicknesses formed in the same chip are equally formed, breakdown of the gate oxide film in the cell array region having a large specific gravity in the chip occurs first. If the breakdown of the gate oxide film in the cell array region occurs first, the semiconductor device may not operate or may lose reliability. In order to solve this problem, the thickness of the gate oxide film in the cell array region is increased to increase the breakdown voltage, and the thickness of the gate oxide film in the peripheral circuit region should be relatively thin to reduce the item voltage. In other words, a semiconductor device having a double gate oxide film having a different thickness of the gate oxide film in the cell array region and the peripheral circuit region can be manufactured to improve the operation characteristics and the reliability of the semiconductor device.
[8] 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a double gate oxide film according to the prior art.
[9] Specifically, in FIGS. 1A to 1D, the left region TK is a region where the gate oxide film is to be formed thick, and the right region TI is a region where the gate oxide film is to be formed thin. As shown in FIG. 1A, the first gate oxide film 13 is formed to a thickness of 10 nm by first oxidizing the semiconductor substrate 10 having the trench 11, for example, a silicon substrate. Subsequently, as shown in FIG. 1B, the photoresist pattern 15 is formed on the first gate oxide layer 13 on the TK region, and then the first gate oxide layer 13 on the TI region is etched. In this case, the thickness of the first gate oxide film 13 on the TI region is reduced.
[10] Subsequently, as shown in FIG. 1C, after the photoresist pattern 15 on the TK region is removed, the first gate oxide layer 13 is etched entirely to remove the first gate oxide layer 13 on the TI region. At this time, the first gate oxide film 13 on the TK region is also etched to reduce the thickness. Next, as shown in FIG. 1D, the semiconductor substrate 10 is secondarily oxidized to form a second gate oxide film 15 on the TI region. At this time, the thickness of the first gate oxide film 13 on the TK region also increases. Through this process, a semiconductor device having a different thickness of the first gate oxide film 13 on the TK region and the second gate oxide film 15 on the TI region, that is, a semiconductor device having a double gate oxide film is completed.
[11] However, in the conventional method of manufacturing a semiconductor device having a double gate oxide film, when the first gate oxide film 13 in the TI region of FIGS. 1B and 1C is selectively removed, the first gate oxide film remaining without being removed in the TK region ( There is a problem in that contamination occurs in 13), the operating characteristics of the semiconductor device is degraded or the yield of the device is lowered.
[12] Accordingly, the present invention has been made in an effort to provide a method of manufacturing a semiconductor device having a double gate oxide film in which the contamination of the gate oxide film does not occur by improving the aforementioned problem.
[1] 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a double gate oxide film according to the prior art.
[2] 2 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a double gate oxide film according to the present invention;
[3] FIG. 13 is a plan view of FIG. 7;
[4] 14A and 14B are cross-sectional views illustrating changes in the thickness of the gate oxide film in the cell array region of FIGS. 8 and 9, respectively.
[13] In order to achieve the above technical problem, the method of manufacturing a semiconductor device of the present invention forms a gate oxide film and a gate pattern on a semiconductor substrate in which a cell array region and a peripheral circuit region are defined. Subsequently, source and drain regions are formed near the surface of the semiconductor substrate between the gate patterns. Subsequently, an interlayer insulating layer pattern having a contact hole exposing the semiconductor substrate of the cell array region is formed while filling the gap between the gate patterns. The semiconductor substrate of the exposed cell array region is oxidized to form a gate oxide layer of the cell array region that is thicker than the gate oxide layer of the peripheral circuit region due to oxygen diffusion. The thickness of the gate oxide film in the cell array region depends on the amount of oxidation during oxidation of the semiconductor substrate. Oxidation of the semiconductor substrate in the exposed cell array region may be performed by a wet oxidation method or a dry oxidation method. Next, a contact pad embedded in the contact hole is formed.
[14] The source and drain regions may be formed in an LDD type. Spacers may be further formed on both sidewalls of the gate pattern and the gate oxide layer. After forming the source and drain regions, an insulating layer having a high etching selectivity with respect to the silicon oxide layer may be further formed on the entire surface of the semiconductor substrate on which the gate pattern is formed.
[15] In the method for manufacturing a semiconductor device having the double gate oxide film of the present invention described above, the gate oxide film in the cell array region can be formed so as not to be contaminated, so that the semiconductor device can have good operating characteristics and improved reliability.
[16] Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, embodiments of the present invention illustrated below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. In the drawings, the size or thickness of films or regions is exaggerated for clarity. In addition, when a film is described as "on" another film or substrate, the film may be directly on top of the other film, and a third other film may be interposed therebetween.
[17] 2 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a double gate oxide film according to the present invention, FIG. 13 is a plan view of FIG. 8, and FIGS. 14A and 14B are respectively shown in FIGS. 8 and 9. A cross-sectional view illustrating a change in thickness of the gate oxide film in the cell array region.
[18] Referring to FIG. 2, a trench oxide layer is formed by performing device isolation on a semiconductor substrate 51, for example, a p-type silicon substrate, in which a cell array region (CA) and a peripheral circuit region (PA) are defined. 53 is formed. The device isolation is performed using a shallow trench isolation (STI) method in this embodiment, but other methods may be used. The portion where the trench oxide film 53 is not formed on the semiconductor substrate 51 becomes an active region.
[19] Subsequently, the well silicon implantation for well formation, the field ion implantation, and the channel ion implantation for channel formation are performed, and then the first silicon oxide film 55 is deposited on the entire surface of the semiconductor substrate 51 for the gate oxide film. Form. The first silicon oxide film 55 is formed of a thermal oxide film, and the thickness of the first silicon oxide film 55 matches the thickness of the gate oxide film to be formed in the peripheral circuit region. For example, the first silicon oxide film is formed to a thickness of 20 to 60 GPa.
[20] Next, a first conductive layer 57 is formed on the first silicon oxide film 55 for the gate electrode. The first conductive layer 57 is formed of a polysilicon film and a metal silicide film doped with impurities to a thickness of 500 to 1000 각각, respectively. Subsequently, a first insulating film 59 is formed on the first conductive layer 57 to a thickness of 1000 to 2000 GPa. The first insulating layer 59 is formed of a material having a high etching selectivity with respect to the silicon oxide layer, for example, a silicon nitride layer.
[21] Referring to FIG. 3, the first insulating layer 59, the first conductive layer 57, and the first silicon oxide layer 55 are patterned using a photolithography process to form the gate pattern 61 and the gate oxide layer 55a. Form. The gate pattern 61 includes a first insulating layer pattern 59a and a gate electrode 57a. Subsequently, N-type impurities are implanted into the entire surface of the semiconductor substrate 51 to form light doped drain (LDD). In this case, the first impurity region 63 is formed near the surface of the semiconductor substrate 51 while being aligned with both sidewalls of the gate pattern 61.
[22] Referring to FIG. 4, spacers 65 are formed on both sidewalls of the gate pattern 61 and the gate oxide layer 55a. The spacer 65 is formed by forming an insulating film 300 to 1000 Å on an entire surface of the semiconductor substrate 51 on which the gate pattern 61 is formed, and then anisotropically etching it. The spacer insulating film is formed using a material having an etching selectivity with respect to a silicon oxide film, for example, a silicon nitride film.
[23] Subsequently, if necessary, thermal oxidation of the semiconductor substrate 51 is performed to thermally oxidize the semiconductor substrate 51 to remove silicon on the damaged semiconductor substrate 51 during anisotropic etching for forming the spacer 65. It may be formed in a thickness. Subsequently, N-type impurities are implanted into the entire surface of the semiconductor substrate 51 on which the gate pattern 61 and the spacer 65 are formed. In this case, the second impurity region 67 is formed near the surface of the semiconductor substrate 51 while being aligned with the spacer 65. As a result, an LDD type source and drain region 68 composed of the first impurity region 63 and the second impurity region 67 is formed.
[24] Referring to FIG. 5, the second insulating layer 69 may be formed on the entire surface of the semiconductor substrate 51 on which the gate pattern 61 and the gate spacer 65 are formed. The second insulating layer 69 is formed using a material having an etching selectivity with respect to the silicon oxide layer, for example, a silicon nitride layer.
[25] Referring to FIG. 6, a third insulating layer 71 is formed on the entire surface of the semiconductor substrate 51 on which the second insulating layer 69 is formed. The third insulating layer 71 is formed using a silicon oxide film having a good gap fill characteristic of filling a narrow and high empty space between the gate patterns.
[26] Referring to FIG. 7, the third insulating film 71 is polished and planarized by chemical mechanical polishing to form an interlayer insulating film 71a. In this case, the thickness of the interlayer insulating layer 71a is adjusted to be within 0 to 1000 kPa on the upper surface of the gate pattern 61.
[27] 8 and 13, the interlayer insulating layer 71a and the second insulating layer 69 of the cell array region CA may be selectively etched using a photolithography process. In this case, the interlayer insulating film pattern 71b and the second insulating film pattern 69a having the contact holes 73 exposing the semiconductor substrate 51 in the cell array region are formed.
[28] The reason for exposing the semiconductor substrate 51 in the cell array region is to form a contact pad later to facilitate electrical contact between the bit line or storage node and the impurity region on the semiconductor substrate. In this regard, a top view is shown in FIG. 13. In FIG. 13, reference numeral 73 denotes a contact hole, reference numeral 75 denotes a gate line, and reference numeral 77 denotes an active region. The size of the contact hole 73 is preferably about 20 to 40 nm larger than the size of the active region 77.
[29] 9, 10, 14A, and 14B, as illustrated in FIG. 9, the semiconductor substrate 51 having the contact hole 73 opening the cell array region CA may be formed by a wet oxidation method or a dry oxidation method. Thermal oxidation. In this case, the second silicon oxide film 79 is formed on the semiconductor substrate 51 in the cell array region with a thickness of 30 to 100 Å. At this time, the gate oxide film 55a in the cell array region as shown in FIG. 14A is changed to the second silicon oxide film 79 in the form of a bird's beak by oxygen diffusion as shown in FIG. 14B. As a result, as shown in FIG. 10, when the second silicon oxide film 79 formed in the cell array region is anisotropically etched, a gate oxide film 55b having a thickness different from that of the peripheral circuit region is formed. The thickness of the gate oxide film 55b of the cell array region depends on the amount of oxidation of the exposed cell array region, and the gate oxide film 55b formed in the cell array region has a corner portion rather than a center portion of the lower portion of the gate pattern 61. This is formed thicker.
[30] If necessary, impurities may be implanted to reduce contact resistance between the impurity regions of the cell array region, that is, the source and drain regions 68 and the contact pads formed later, before the anisotropic etching of the second silicon oxide layer 79. .
[31] Referring to FIG. 11, the second conductive layer 81 for contact pads is formed on the entire surface of the semiconductor substrate 51 so as to fill the contact holes 73 in the cell array region with a thickness of 3000 to 5000 kPa. The second conductive layer 81 is formed using a polysilicon film doped with impurities.
[32] Referring to FIG. 12, the contact pads 81a and 81b are formed by grinding and planarizing the second conductive layer 81 for contact pads by chemical mechanical polishing. The polishing stop point (etch stop point) during the polishing of the second conductive layer 81 is adjusted to the upper surface of the gate pattern 61. The contact pad 81a is connected to a bit line in a subsequent process, and the contact pad 81b is connected to a storage node of a capacitor.
[33] As described above, the method of manufacturing a semiconductor device having a double gate oxide film according to the present invention oxidizes a semiconductor substrate in an exposed cell array region, thereby oxidizing a gate oxide film in a cell array region thicker than the gate oxide layer in a peripheral circuit region due to oxygen diffusion. Form. As a result, in the method of manufacturing the semiconductor device of the present invention, since the gate oxide film in the cell array region can be formed so as not to be contaminated, the semiconductor device can have good operating characteristics and improved reliability.

权利要求:
Claims (10)
[1" claim-type="Currently amended] Forming a gate oxide film and a gate pattern on the semiconductor substrate in which the cell array region and the peripheral circuit region are defined;
Forming a source and a drain region near a surface of the semiconductor substrate between the gate patterns;
Forming an interlayer insulating layer pattern having a contact hole exposing a semiconductor substrate in the cell array region while filling the gap between the gate patterns;
Oxidizing the semiconductor substrate in the exposed cell array region to form a gate oxide layer in the cell array region that is thicker than the gate oxide layer in the peripheral circuit region due to oxygen diffusion; And
And forming a contact pad buried in the contact hole.
[2" claim-type="Currently amended] The method of claim 1, wherein the source and drain regions are of an LDD type.
[3" claim-type="Currently amended] The method of claim 1, wherein spacers are formed on both sidewalls of the gate pattern and the gate oxide film.
[4" claim-type="Currently amended] The method of claim 1, further comprising, after forming the source and drain regions, an insulating layer having a high etch selectivity with respect to a silicon oxide layer on an entire surface of the semiconductor substrate on which the gate pattern is formed.
[5" claim-type="Currently amended] The method of claim 4, wherein the insulating film is a silicon nitride film.
[6" claim-type="Currently amended] The method of claim 1, wherein the forming of the interlayer insulating film pattern exposing the semiconductor substrate in the cell array region comprises: forming an insulating film on the entire surface of the semiconductor substrate so as to fill the gate patterns, and planarizing the insulating film. Forming an interlayer insulating film, and selectively etching the interlayer insulating film in the cell array region using a photolithography process.
[7" claim-type="Currently amended] 7. The method of claim 6, wherein the thickness of the interlayer insulating film is adjusted within 0 to 1000 kW from the upper surface of the gate pattern when the insulating film is planarized to form the interlayer insulating film.
[8" claim-type="Currently amended] The method of claim 1, wherein the semiconductor substrate of the exposed cell array region is oxidized by a wet oxidation method or a dry oxidation method.
[9" claim-type="Currently amended] The method of claim 1, wherein the contact pad comprises forming a conductive layer on an entire surface of the semiconductor substrate to fill the contact hole, and planarizing the conductive layer using an upper surface of the gate pattern as an etch stop. A method of manufacturing a semiconductor device, characterized in that.
[10" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the gate oxide film in the cell array region depends on the amount of oxidation during oxidation of the semiconductor substrate.

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2001-06-28|Application filed by 삼성전자 주식회사

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2001-06-28|Priority to KR1020010037634A

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2003-01-08|Publication of KR20030001827A

优先权:

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申请号 | 申请日 | 专利标题

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KR1020010037634A|KR20030001827A|2001-06-28|2001-06-28|Fabrication method of semiconductor device having dual gate oxide layer|